SaciSlaveRam.rtl Architecture Reference

Architecture >> SaciSlaveRam::rtl

Processes
p
p

Types
RamType	( 0 to 2 ** 19 ) slv ( 31 downto 0 )

Signals
ram	RamType := ( others = > X " 00000000 " )

---

The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/SaciSlaveRam.vhd
• protocols/saci/saci1/sim/SaciSlaveRam.vhd