SaciMultiPixel Entity Reference

Entities
SaciMultiPixel.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
SaciMultiPixelPkg	Package <SaciMultiPixelPkg>

Generics
TPD_G	time := 1 ns
MASK_REG_ADDR_G	slv ( 31 downto 0 ) := x " 00000034 "
SACI_BASE_ADDR_G	slv ( 31 downto 0 ) := x " 02000000 "
SACI_NUM_CHIPS_G	natural range 1 to 4 := 4

Ports
axilClk	in	sl
axilRst	in	sl
sAxilWriteMaster	in	AxiLiteWriteMasterType
sAxilWriteSlave	out	AxiLiteWriteSlaveType
sAxilReadMaster	in	AxiLiteReadMasterType
sAxilReadSlave	out	AxiLiteReadSlaveType
mAxilWriteMaster	out	AxiLiteWriteMasterType
mAxilWriteSlave	in	AxiLiteWriteSlaveType
mAxilReadMaster	out	AxiLiteReadMasterType
mAxilReadSlave	in	AxiLiteReadSlaveType

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/SaciMultiPixel.vhd
• protocols/saci/saci1/rtl/SaciMultiPixel.vhd