SaciAxiLiteMasterTbWrapper.mapping Architecture Reference

Architecture >> SaciAxiLiteMasterTbWrapper::mapping

Processes
PROCESS_157
PROCESS_373

Signals
axilClk	sl
axilRstL	sl
axilReadMaster	AxiLiteReadMasterType
axilReadSlave	AxiLiteReadSlaveType
axilWriteMaster	AxiLiteWriteMasterType
axilWriteSlave	AxiLiteWriteSlaveType

Instantiations
u_saciaxilitemastertb_1	SaciAxiLiteMasterTb <Entity SaciAxiLiteMasterTb>
u_clkrst_2	ClkRst <Entity ClkRst>
u_saciaxilitemastertb_1	SaciAxiLiteMasterTb <Entity SaciAxiLiteMasterTb>
u_clkrst_2	ClkRst <Entity ClkRst>

---

The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/SaciAxiLiteMasterTbWrapper.vhd
• protocols/saci/saci1/sim/SaciAxiLiteMasterTbWrapper.vhd