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RogueTcpMemoryWrap Entity Reference
Inheritance diagram for RogueTcpMemoryWrap: Collaboration diagram for RogueTcpMemoryWrap:Entities | |
| RogueTcpMemoryWrap.RogueTcpMemoryWrap | architecture |
Libraries | |
| ieee | |
| surf | |
Use Clauses | |
| std_logic_1164 | |
| std_logic_arith | |
| std_logic_unsigned | |
| StdRtlPkg | Package <StdRtlPkg> |
| AxiLitePkg | Package <AxiLitePkg> |
Generics | |
| TPD_G | time := 1 ns |
| PORT_NUM_G | natural range 1024 to 49151 := 9000 |
Ports | ||
| axilClk | in | sl |
| axilRst | in | sl |
| axilReadMaster | out | AxiLiteReadMasterType |
| axilReadSlave | in | AxiLiteReadSlaveType |
| axilWriteMaster | out | AxiLiteWriteMasterType |
| axilWriteSlave | in | AxiLiteWriteSlaveType |
The documentation for this design unit was generated from the following files:
- axi/simlink/sim/RogueTcpMemoryWrap.vhd
- build/SRC_VHDL/surf/RogueTcpMemoryWrap.vhd
