RoceResizeAndSwap.rtl Architecture Reference

Architecture >> RoceResizeAndSwap::rtl

Functions
std_logic_vector	ChangeEndian ( vec: in std_logic_vector )
std_logic_vector	ReverseBits ( vec: in std_logic_vector )

Processes
comb	( pipeAxisSlave , r , sAxisMaster , sSideBand )
seq	( axisClk , axisRst )

Constants
SLV_BYTES_C	positive := SLAVE_AXI_CONFIG_G.TDATA_BYTES_C
MST_BYTES_C	positive := MASTER_AXI_CONFIG_G.TDATA_BYTES_C
SLV_USER_C	positive := ite ( SLAVE_AXI_CONFIG_G.TUSER_BITS_C/ = 0 , SLAVE_AXI_CONFIG_G.TUSER_BITS_C , 1 )
MST_USER_C	positive := ite ( MASTER_AXI_CONFIG_G.TUSER_BITS_C/ = 0 , MASTER_AXI_CONFIG_G.TUSER_BITS_C , 1 )
COUNT_C	positive := ite ( SLV_BYTES_C> MST_BYTES_C , SLV_BYTES_C/ MST_BYTES_C , MST_BYTES_C/ SLV_BYTES_C )
REG_INIT_C	RegType := ( count = > ( others = > ' 0 ' ) , obMaster = > axiStreamMasterInit ( MASTER_AXI_CONFIG_G ) , sideBand = > ( others = > ' 0 ' ) , ibSlave = > AXI_STREAM_SLAVE_INIT_C )

Signals
r	RegType := REG_INIT_C
rin	RegType
pipeAxisMaster	AxiStreamMasterType
pipeSideBand	slv ( SIDE_BAND_WIDTH_G- 1 downto 0 )
pipeAxisSlave	AxiStreamSlaveType

Records
RegType

Instantiations
axistreampipeline_1	AxiStreamPipeline <Entity AxiStreamPipeline>

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The documentation for this design unit was generated from the following file:

• ethernet/RoCEv2/rtl/RoceResizeAndSwap.vhd