RoceEngineWrapper Entity Reference

Inheritance diagram for RoceEngineWrapper:

Collaboration diagram for RoceEngineWrapper:

Entities
RoceEngineWrapper.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
AxiLitePkg	Package <AxiLitePkg>
SsiPkg	Package <SsiPkg>
RocePkg	Package <RocePkg>

Generics
TPD_G	time := 1 ns
EXT_ROCE_CONFIG_G	boolean := false

Ports
clk	in	sl
rst	in	sl
workReqMaster	in	RoceWorkReqMasterType
workReqSlave	out	RoceWorkReqSlaveType
workCompMaster	out	RoceWorkCompMasterType
workCompSlave	in	RoceWorkCompSlaveType
obUdpMaster	in	AxiStreamMasterType
obUdpSlave	out	AxiStreamSlaveType
ibUdpMaster	out	AxiStreamMasterType
ibUdpSlave	in	AxiStreamSlaveType
sAxisMetaDataMaster	in	AxiStreamMasterType
sAxisMetaDataSlave	out	AxiStreamSlaveType
mAxisMetaDataMaster	out	AxiStreamMasterType
mAxisMetaDataSlave	in	AxiStreamSlaveType
axilReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	out	AxiLiteWriteSlaveType
dmaReadRespMaster	in	RoceDmaReadRespMasterType
dmaReadRespSlave	out	RoceDmaReadRespSlaveType
dmaReadReqMaster	out	RoceDmaReadReqMasterType
dmaReadReqSlave	in	RoceDmaReadReqSlaveType

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The documentation for this design unit was generated from the following file:

• ethernet/RoCEv2/rtl/RoceEngineWrapper.vhd