Architecture >> RoceConfiguratorWrapper::rtl

Processes
mMetaReqView	( mMetaReqMaster )
sMetaRespComb	( S_META_RESP_TDATA , S_META_RESP_TVALID )

Signals
axilClk	sl
axilRst	sl
axilReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
axilWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C
mMetaReqMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
mMetaReqSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C
sMetaRespMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
sMetaRespSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C

Instantiations
u_shimlayer	SlaveAxiLiteIpIntegrator <Entity SlaveAxiLiteIpIntegrator>
u_dut	RoceConfigurator <Entity RoceConfigurator>

The documentation for this design unit was generated from the following file:

Processes

Signals