RoCEv2AlphaUpdate.rtl Architecture Reference

Architecture >> RoCEv2AlphaUpdate::rtl

Processes
comb	( AlphaG , alphaUpdInterval , cnpDetected , curAlpha , r , rst , start )
seq	( clk , rst )

Constants
ONE_FP_C	std_logic_vector ( 10 downto 0 ) := " 10000000000 "
REG_INIT_C	RegType := ( timer = > ( others = > ' 0 ' ) , newAlpha = > ( others = > ' 0 ' ) , valid = > ' 0 ' , state = > IDLE_S )

Types
StateType	( IDLE_S , COUNTING_S , UPDATE_S )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following file:

• ethernet/RoCEv2/rtl/RoCEv2AlphaUpdate.vhd