PwrUpRst.rtl Architecture Reference

Architecture >> PwrUpRst::rtl

Processes
PROCESS_36	( clk , rstSync )
PROCESS_145	( clk , rstSync )

Constants
CNT_SIZE_C	natural := ite ( SIM_SPEEDUP_G , 127 , DURATION_G )

Signals
rstSync	sl := OUT_POLARITY_G
rst	sl := OUT_POLARITY_G
cnt	natural range 0 to DURATION_G := 0

Attributes
use_dsp	string
use_dsp	signal is USE_DSP_G

Instantiations
rstsync_inst	RstSync <Entity RstSync>
rstsync_inst	RstSync <Entity RstSync>

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The documentation for this design unit was generated from the following files:

• base/general/rtl/PwrUpRst.vhd
• build/SRC_VHDL/surf/PwrUpRst.vhd