PgpParallelSimModel Entity Reference

Inheritance diagram for PgpParallelSimModel:

Collaboration diagram for PgpParallelSimModel:

Entities
PgpParallelSimModel.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
Pgp2bPkg	Package <Pgp2bPkg>
AxiStreamPkg	Package <AxiStreamPkg>

Generics
TPD_G	time := 1 ns
CLK_FREQ_G	real := 156 . 250E + 6
CABLE_LENGTH_G	real := 1 . 0
INDEX_OF_REFRACTION_G	real := 1 . 5
TX_SER_DELAY_C	natural := 5
RX_SER_DELAY_C	natural := 5
VC_INTERLEAVE_G	integer := 1
PAYLOAD_CNT_TOP_G	integer := 7
NUM_VC_EN_G	integer range 1 to 4 := 4
TX_ENABLE_G	boolean := true
RX_ENABLE_G	boolean := true

Ports
clk	in	sl
rst	in	sl
pgpTxMasters	in	AxiStreamMasterArray ( 3 downto 0 )
pgpTxSlaves	out	AxiStreamSlaveArray ( 3 downto 0 )
pgpRxMasters	out	AxiStreamMasterArray ( 3 downto 0 )
pgpRxCtrl	in	AxiStreamCtrlArray ( 3 downto 0 )
pgpRxIn	in	Pgp2bRxInType := PGP2B_RX_IN_INIT_C
pgpRxOut	out	Pgp2bRxOutType
pgpTxIn	in	Pgp2bTxInType := PGP2B_TX_IN_INIT_C
pgpTxOut	out	Pgp2bTxOutType
pgpIn	in	slv ( 19 downto 0 )
pgpOut	out	slv ( 19 downto 0 )

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The documentation for this design unit was generated from the following file:

• protocols/pgp/pgp2b/core/tb/PgpParallelSimModel.vhd