Pgp4TxLiteWrapper Entity Reference

Inheritance diagram for Pgp4TxLiteWrapper:

Collaboration diagram for Pgp4TxLiteWrapper:

Entities
Pgp4TxLiteWrapper.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
Pgp4Pkg	Package <Pgp4Pkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false

Ports
clk	in	sl
rst	in	sl
txValid	in	sl
txReady	out	sl
txData	in	slv ( 63 downto 0 )
txSof	in	sl
txEof	in	sl
txEofe	in	sl
phyTxValid	out	sl
phyTxReady	in	sl
phyTxData	out	slv ( 65 downto 0 )

---

The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/Pgp4TxLiteWrapper.vhd
• protocols/pgp/pgp4/core/rtl/Pgp4TxLiteWrapper.vhd