Architecture >> Pgp4GtyUsWrapper::rtl
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NUM_AXIL_MASTERS_C | integer := NUM_LANES_G+ 1 |
QPLL_AXIL_INDEX_C | integer := NUM_AXIL_MASTERS_C- 1 |
XBAR_CONFIG_C | AxiLiteCrossbarMasterConfigArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := genAxiLiteConfig ( NUM_AXIL_MASTERS_C , AXIL_BASE_ADDR_G , 16 , 13 ) |
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qpllLock | Slv2Array ( 3 downto 0 ) := ( others = > " 00 " ) |
qpllClk | Slv2Array ( 3 downto 0 ) := ( others = > " 00 " ) |
qpllRefclk | Slv2Array ( 3 downto 0 ) := ( others = > " 00 " ) |
qpllRst | Slv2Array ( 3 downto 0 ) := ( others = > " 00 " ) |
pgpRefClkDiv2 | sl |
pgpRefClk | sl |
axilReadMasters | AxiLiteReadMasterArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := ( others = > AXI_LITE_READ_MASTER_INIT_C ) |
axilReadSlaves | AxiLiteReadSlaveArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := ( others = > AXI_LITE_READ_SLAVE_EMPTY_DECERR_C ) |
axilWriteMasters | AxiLiteWriteMasterArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := ( others = > AXI_LITE_WRITE_MASTER_INIT_C ) |
axilWriteSlaves | AxiLiteWriteSlaveArray ( NUM_AXIL_MASTERS_C- 1 downto 0 ) := ( others = > AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C ) |
The documentation for this design unit was generated from the following file:
- protocols/pgp/pgp4/gtyUs+/rtl/Pgp4GtyUsWrapper.vhd