Pgp4Gtx7Wrapper Entity Reference

Inheritance diagram for Pgp4Gtx7Wrapper:

Collaboration diagram for Pgp4Gtx7Wrapper:

Entities
Pgp4Gtx7Wrapper.rtl	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
AxiLitePkg	Package <AxiLitePkg>
Pgp4Pkg	Package <Pgp4Pkg>
vcomponents

Generics
TPD_G	time := 1 ns
ROGUE_SIM_EN_G	boolean := false
ROGUE_SIM_SIDEBAND_G	boolean := true
ROGUE_SIM_PORT_NUM_G	natural range 1024 to 49151 := 9000
NUM_LANES_G	positive range 1 to 4 := 1
NUM_VC_G	positive range 1 to 16 := 4
RATE_G	string := " 10.3125Gbps "
REFCLK_FREQ_G	real := 312 . 5E + 6
REFCLK_G	boolean := false
PGP_RX_ENABLE_G	boolean := true
RX_ALIGN_SLIP_WAIT_G	integer := 32
PGP_TX_ENABLE_G	boolean := true
TX_CELL_WORDS_MAX_G	integer := PGP4_DEFAULT_TX_CELL_WORDS_MAX_C
TX_MUX_MODE_G	string := " INDEXED "
TX_MUX_TDEST_ROUTES_G	Slv8Array := ( 0 = > " -------- " )
TX_MUX_TDEST_LOW_G	integer range 0 to 7 := 0
TX_MUX_ILEAVE_EN_G	boolean := true
TX_MUX_ILEAVE_ON_NOTVALID_G	boolean := true
EN_PGP_MON_G	boolean := false
EN_GT_DRP_G	boolean := false
EN_QPLL_DRP_G	boolean := false
WRITE_EN_G	boolean := true
TX_POLARITY_G	slv ( 3 downto 0 ) := x " 0 "
RX_POLARITY_G	slv ( 3 downto 0 ) := x " 0 "
STATUS_CNT_WIDTH_G	natural range 1 to 32 := 16
ERROR_CNT_WIDTH_G	natural range 1 to 32 := 8
AXIL_BASE_ADDR_G	slv ( 31 downto 0 ) := ( others = > ' 0 ' )
AXIL_CLK_FREQ_G	real := 156 . 25E + 6

Ports
stableClk	in	sl
stableRst	in	sl
pgpGtTxP	out	slv ( NUM_LANES_G- 1 downto 0 )
pgpGtTxN	out	slv ( NUM_LANES_G- 1 downto 0 )
pgpGtRxP	in	slv ( NUM_LANES_G- 1 downto 0 )
pgpGtRxN	in	slv ( NUM_LANES_G- 1 downto 0 )
pgpRefClkP	in	sl := ' 0 '
pgpRefClkN	in	sl := ' 1 '
pgpRefClkIn	in	sl := ' 0 '
pgpRefClkOut	out	sl
pgpRefClkDiv2Bufg	out	sl
pgpClk	out	slv ( NUM_LANES_G- 1 downto 0 )
pgpClkRst	out	slv ( NUM_LANES_G- 1 downto 0 )
pgpRxIn	in	Pgp4RxInArray ( NUM_LANES_G- 1 downto 0 )
pgpRxOut	out	Pgp4RxOutArray ( NUM_LANES_G- 1 downto 0 )
pgpTxIn	in	Pgp4TxInArray ( NUM_LANES_G- 1 downto 0 )
pgpTxOut	out	Pgp4TxOutArray ( NUM_LANES_G- 1 downto 0 )
pgpTxMasters	in	AxiStreamMasterArray ( ( NUM_LANES_G* NUM_VC_G ) - 1 downto 0 )
pgpTxSlaves	out	AxiStreamSlaveArray ( ( NUM_LANES_G* NUM_VC_G ) - 1 downto 0 )
pgpRxMasters	out	AxiStreamMasterArray ( ( NUM_LANES_G* NUM_VC_G ) - 1 downto 0 )
pgpRxCtrl	in	AxiStreamCtrlArray ( ( NUM_LANES_G* NUM_VC_G ) - 1 downto 0 )
pgpRxSlaves	in	AxiStreamSlaveArray ( ( NUM_LANES_G* NUM_VC_G ) - 1 downto 0 ) := ( others = > AXI_STREAM_SLAVE_FORCE_C )
axilClk	in	sl := ' 0 '
axilRst	in	sl := ' 0 '
axilReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	out	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_EMPTY_DECERR_C
axilWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	out	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C

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The documentation for this design unit was generated from the following file:

• protocols/pgp/pgp4/gtx7/rtl/Pgp4Gtx7Wrapper.vhd