Pgp3RxGearboxAligner Entity Reference

Inheritance diagram for Pgp3RxGearboxAligner:

Entities
Pgp3RxGearboxAligner.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
SLIP_WAIT_G	integer := 32

Ports
clk	in	sl
rst	in	sl
rxHeader	in	slv ( 1 downto 0 )
rxHeaderValid	in	sl
slip	out	sl
locked	out	sl

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/Pgp3RxGearboxAligner.vhd
• protocols/pgp/pgp3/core/rtl/Pgp3RxGearboxAligner.vhd