Inheritance diagram for Pgp3GtyUs:

Collaboration diagram for Pgp3GtyUs:

Generics
TPD_G	time := 1 ns
RATE_G	string := " 10.3125Gbps "
SYNTH_MODE_G	string := " inferred "
PGP_RX_ENABLE_G	boolean := true
RX_ALIGN_SLIP_WAIT_G	integer := 32
PGP_TX_ENABLE_G	boolean := true
NUM_VC_G	integer range 1 to 16 := 4
TX_CELL_WORDS_MAX_G	integer := PGP3_DEFAULT_TX_CELL_WORDS_MAX_C
TX_MUX_MODE_G	string := " INDEXED "
TX_MUX_TDEST_ROUTES_G	Slv8Array := ( 0 = > " -------- " )
TX_MUX_TDEST_LOW_G	integer range 0 to 7 := 0
TX_MUX_ILEAVE_EN_G	boolean := true
TX_MUX_ILEAVE_ON_NOTVALID_G	boolean := true
EN_DRP_G	boolean := false
EN_PGP_MON_G	boolean := false
TX_POLARITY_G	sl := ' 0 '
RX_POLARITY_G	sl := ' 0 '
AXIL_BASE_ADDR_G	slv ( 31 downto 0 ) := ( others = > ' 0 ' )
AXIL_CLK_FREQ_G	real := 125 . 0E + 6

Ports
stableClk	in	sl
stableRst	in	sl
qpllLock	in	slv ( 1 downto 0 )
qpllclk	in	slv ( 1 downto 0 )
qpllrefclk	in	slv ( 1 downto 0 )
qpllRst	out	slv ( 1 downto 0 )
pgpGtTxP	out	sl
pgpGtTxN	out	sl
pgpGtRxP	in	sl
pgpGtRxN	in	sl
pgpClk	out	sl
pgpClkRst	out	sl
pgpRxIn	in	Pgp3RxInType
pgpRxOut	out	Pgp3RxOutType
pgpTxIn	in	Pgp3TxInType
pgpTxOut	out	Pgp3TxOutType
pgpTxMasters	in	AxiStreamMasterArray ( NUM_VC_G- 1 downto 0 )
pgpTxSlaves	out	AxiStreamSlaveArray ( NUM_VC_G- 1 downto 0 )
pgpRxMasters	out	AxiStreamMasterArray ( NUM_VC_G- 1 downto 0 )
pgpRxCtrl	in	AxiStreamCtrlArray ( NUM_VC_G- 1 downto 0 )
axilClk	in	sl := ' 0 '
axilRst	in	sl := ' 0 '
axilReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	out	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_EMPTY_DECERR_C
axilWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	out	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C

The documentation for this design unit was generated from the following file:

Entities

Libraries