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Pgp3Gtx7Qpll.mapping Architecture Reference
Architecture >> Pgp3Gtx7Qpll::mapping

Functions

integer   GenQpllfbdivTop
bit_vector   GenQplFfbdivTop ( qpllfbdivTop: in in positive[ impure ]
bit   GenQpllFbdivRatio ( qpllfbdivTop: in in positive[ impure ]
integer   GenRefclkDiv

Constants

QPLL_CFG_C  bit_vector := ite ( ( RATE_G = " 10.3125Gbps " ) , x " 0680181 " , x " 06801C1 " )
QPLL_FBDIV_TOP_C  positive := GenQpllfbdivTop
QPLL_FBDIV_C  bit_vector := GenQplFfbdivTop ( QPLL_FBDIV_TOP_C )
QPLL_FBDIV_RATIO_C  bit := GenQpllFbdivRatio ( QPLL_FBDIV_TOP_C )
QPLL_REFCLK_DIV_C  positive := GenRefclkDiv

Signals

pllOutClk  sl
pllOutRefClk  sl
pllLock  sl
pllRefClkLost  sl
pllReset  sl
lockedStrobe  slv ( 3 downto 0 )
gtQPllReset  slv ( 3 downto 0 )

Instantiations

u_pwruprst  PwrUpRst <Entity PwrUpRst>
u_qpll  Gtx7QuadPll <Entity Gtx7QuadPll>

The documentation for this design unit was generated from the following file: