Pgp3Gtx7IpWrapper.mapping Architecture Reference

Architecture >> Pgp3Gtx7IpWrapper::mapping

Processes
PROCESS_348	( txUsrClk2Int )

Components
Pgp3Gtx7Ip10G
Pgp3Gtx7Ip6G
Pgp3Gtx7Ip3G

Signals
gtRxOutClk	sl
gtRxPllRst	sl
gtRxPllLock	sl
rxPllClk	slv ( 1 downto 0 )
rxPllRst	slv ( 1 downto 0 )
rxUsrClkInt	sl
rxUsrClk2Int	sl
txUsrClkInt	sl
txUsrClk2Int	sl
drpAddr	slv ( 8 downto 0 ) := ( others = > ' 0 ' )
drpDi	slv ( 15 downto 0 ) := ( others = > ' 0 ' )
drpDo	slv ( 15 downto 0 ) := ( others = > ' 0 ' )
drpEn	sl := ' 0 '
drpWe	sl := ' 0 '
drpRdy	sl := ' 0 '
txGearBoxReady	sl := ' 0 '
txGearBoxReadyDly	sl := ' 0 '

Instantiations
u_rx_pll	ClockManager7 <Entity ClockManager7>
u_pgp3gtx7ip10g	pgp3gtx7ip10g
u_pgp3gtx7ip6g	pgp3gtx7ip6g
u_pgp3gtx7ip3g	pgp3gtx7ip3g
u_axilitetodrp_1	AxiLiteToDrp <Entity AxiLiteToDrp>

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The documentation for this design unit was generated from the following file:

• protocols/pgp/pgp3/gtx7/rtl/Pgp3Gtx7IpWrapper.vhd