Pgp3GthUsQpll Entity Reference

Inheritance diagram for Pgp3GthUsQpll:

Collaboration diagram for Pgp3GthUsQpll:

Entities
Pgp3GthUsQpll.mapping	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
vcomponents
Pgp3Pkg	Package <Pgp3Pkg>

Generics
TPD_G	time := 1 ns
RATE_G	string := " 10.3125Gbps "
EN_DRP_G	boolean := true
REFCLK_FREQ_G	real := 156 . 25E + 6
QPLL_REFCLK_SEL_G	slv ( 2 downto 0 ) := " 001 "

Ports
stableClk	in	sl
stableRst	in	sl
pgpRefClk	in	sl
qpllLock	out	Slv2Array ( 3 downto 0 )
qpllClk	out	Slv2Array ( 3 downto 0 )
qpllRefclk	out	Slv2Array ( 3 downto 0 )
qpllRst	in	Slv2Array ( 3 downto 0 )
axilClk	in	sl := ' 0 '
axilRst	in	sl := ' 0 '
axilReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	out	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_EMPTY_DECERR_C
axilWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	out	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C

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The documentation for this design unit was generated from the following files:

• protocols/pgp/pgp3/gthUs+/rtl/Pgp3GthUsQpll.vhd
• protocols/pgp/pgp3/gthUs/rtl/Pgp3GthUsQpll.vhd