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Pgp2fcTxPhy.Pgp2fcTxPhy Architecture Reference
Architecture >> Pgp2fcTxPhy::Pgp2fcTxPhy

Processes

PROCESS_329  ( pgpTxClk )
PROCESS_330  ( pgpTxClk )
PROCESS_331  ( cellData , cellDataK , cellTxEOC , curState , fcData , fcDataK , fcValid , fcWordCount , holdState , intTxLinkReady , ltsAData , ltsADataK , ltsBData , ltsBDataK )
fcComb  ( crcOut , fcWordCount , fcWordLatch )
PROCESS_332  ( pgpTxClk )

Types

FsmState  ( ST_LOCK_C , ST_LTS_A_C , ST_LTS_B_C , ST_FC_C , ST_CELL_C , ST_EMPTY_C )

Signals

intTxLinkReady  sl := ' 0 '
nxtTxLinkReady  sl
nxtTxData  slv ( 15 downto 0 )
nxtTxDataK  slv ( 1 downto 0 )
intTxData  slv ( 15 downto 0 ) := ( others = > ' 0 ' )
intTxDataK  slv ( 1 downto 0 ) := ( others = > ' 0 ' )
ltsAData  slv ( 15 downto 0 )
ltsADataK  slv ( 1 downto 0 )
ltsBData  slv ( 15 downto 0 )
ltsBDataK  slv ( 1 downto 0 )
cellData  slv ( 15 downto 0 )
cellDataK  slv ( 1 downto 0 )
fcData  slv ( 15 downto 0 )
fcDataK  slv ( 1 downto 0 )
fcWordLatch  slv ( 16 * FC_WORDS_G- 1 downto 0 ) := ( others = > ' 0 ' )
fcWordCount  integer range 0 to FC_WORDS_G := 0
crcRst  sl
crcEn  sl
crcDataIn  slv ( 15 downto 0 )
crcOut  slv ( 7 downto 0 )
curState  FsmState := ST_LOCK_C
nxtState  FsmState
pendState  FsmState
holdState  FsmState

Instantiations

u_crc7  CRC7Rtl <Entity CRC7Rtl>

The documentation for this design unit was generated from the following file: