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CRC7Rtl Entity Reference
+ Inheritance diagram for CRC7Rtl:

Entities

CRC7Rtl.imp_crc  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 

Ports

rst   in   std_logic
clk   in   std_logic
data_in   in   std_logic_vector ( 15 downto 0 )
crc_en   in   std_logic
crc_out   out   std_logic_vector ( 7 downto 0 )
crc_out_r   out   std_logic_vector ( 7 downto 0 )

The documentation for this design unit was generated from the following file: