Pgp2fcGtyCoreWrapper Entity Reference

Inheritance diagram for Pgp2fcGtyCoreWrapper:

Collaboration diagram for Pgp2fcGtyCoreWrapper:

Entities
Pgp2fcGtyCoreWrapper.mapping	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
vcomponents

Generics
TPD_G	time := 1 ns
SIMULATION_G	boolean := false
SEL_FABRIC_REFCLK_G	boolean := false
USE_ALIGN_CHECK_G	boolean := true
AXI_CLK_FREQ_G	real := 125 . 0E + 6
AXI_BASE_ADDR_G	slv ( 31 downto 0 ) := ( others = > ' 0 ' )

Ports
stableClk	in	sl
stableRst	in	sl
gtRefClk	in	sl
gtFabricRefClk	in	sl
gtUserRefClk	in	sl
gtRxP	in	sl
gtRxN	in	sl
gtTxP	out	sl
gtTxN	out	sl
phyRxReady	out	sl
rxReset	in	sl
rxUsrClkActive	in	sl
rxResetDone	out	sl
rxPmaResetDone	out	sl
rxUsrClk	in	sl
rxData	out	slv ( 15 downto 0 )
rxDataK	out	slv ( 1 downto 0 )
rxDispErr	out	slv ( 1 downto 0 )
rxDecErr	out	slv ( 1 downto 0 )
rxPolarity	in	sl
rxOutClk	out	sl
txReset	in	sl
txUsrClk	in	sl
txUsrClkActive	in	sl
txResetDone	out	sl
txData	in	slv ( 15 downto 0 )
txDataK	in	slv ( 1 downto 0 )
txPolarity	in	sl
txOutClk	out	sl
loopback	in	slv ( 2 downto 0 )
axilClk	in	sl := ' 0 '
axilRst	in	sl := ' 0 '
axilReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	out	AxiLiteWriteSlaveType

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The documentation for this design unit was generated from the following file:

• protocols/pgp/pgp2fc/gtyUltraScale+/rtl/Pgp2fcGtyCoreWrapper.vhd