Pgp2bGtyUltra Entity Reference

Inheritance diagram for Pgp2bGtyUltra:

Collaboration diagram for Pgp2bGtyUltra:

Entities
Pgp2bGtyUltra.mapping	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
numeric_std
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
AxiLitePkg	Package <AxiLitePkg>
Pgp2bPkg	Package <Pgp2bPkg>
vcomponents

Generics
TPD_G	time := 1 ns
TX_POLARITY_G	sl := ' 0 '
RX_POLARITY_G	sl := ' 0 '
TX_ENABLE_G	boolean := true
RX_ENABLE_G	boolean := true
PAYLOAD_CNT_TOP_G	integer := 7
VC_INTERLEAVE_G	integer := 0
NUM_VC_EN_G	integer range 1 to 4 := 4

Ports
stableClk	in	sl
stableRst	in	sl
gtRefClk	in	sl
pgpGtTxP	out	sl
pgpGtTxN	out	sl
pgpGtRxP	in	sl
pgpGtRxN	in	sl
pgpTxReset	in	sl
pgpTxResetDone	out	sl
pgpTxOutClk	out	sl
pgpTxClk	in	sl
pgpTxMmcmLocked	in	sl
pgpRxReset	in	sl
pgpRxResetDone	out	sl
pgpRxOutClk	out	sl
pgpRxClk	in	sl
pgpRxMmcmLocked	in	sl
pgpRxIn	in	Pgp2bRxInType
pgpRxOut	out	Pgp2bRxOutType
pgpTxIn	in	Pgp2bTxInType
pgpTxOut	out	Pgp2bTxOutType
pgpTxMasters	in	AxiStreamMasterArray ( 3 downto 0 ) := ( others = > AXI_STREAM_MASTER_INIT_C )
pgpTxSlaves	out	AxiStreamSlaveArray ( 3 downto 0 )
pgpRxMasters	out	AxiStreamMasterArray ( 3 downto 0 )
pgpRxMasterMuxed	out	AxiStreamMasterType
pgpRxCtrl	in	AxiStreamCtrlArray ( 3 downto 0 )
axilClk	in	sl := ' 0 '
axilRst	in	sl := ' 0 '
axilReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	out	AxiLiteWriteSlaveType

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The documentation for this design unit was generated from the following file:

• protocols/pgp/pgp2b/gtyUltraScale+/rtl/Pgp2bGtyUltra.vhd