Pgp2bGtx7VarLatWrapperTb.tb Architecture Reference

Architecture >> Pgp2bGtx7VarLatWrapperTb::tb

Constants
TPD_G	time := 1 ns
CLKIN_PERIOD_G	real := 16 . 0
DIVCLK_DIVIDE_G	natural range 1 to 106 := 2
CLKFBOUT_MULT_F_G	real range 1 . 0 to 64 . 0 := 31 . 875
CLKOUT0_DIVIDE_F_G	real range 1 . 0 to 128 . 0 := 6 . 375
CPLL_REFCLK_SEL_G	bit_vector := " 001 "
CPLL_FBDIV_G	natural := 5
CPLL_FBDIV_45_G	natural := 5
CPLL_REFCLK_DIV_G	natural := 1
RXOUT_DIV_G	natural := 2
TXOUT_DIV_G	natural := 2
RX_CLK25_DIV_G	natural := 5
TX_CLK25_DIV_G	natural := 5
RX_OS_CFG_G	bit_vector := " 0000010000000 "
RXCDR_CFG_G	bit_vector := x " 03000023FF40200020 "
RXDFEXYDEN_G	sl := ' 1 '
RX_DFE_KL_CFG2_G	bit_vector := x " 301148AC "
TX_BUF_EN_G	boolean := true
TX_OUTCLK_SRC_G	string := " OUTCLKPMA "
TX_DLY_BYPASS_G	sl := ' 1 '
TX_PHASE_ALIGN_G	string := " NONE "
VC_INTERLEAVE_G	integer := 0
PAYLOAD_CNT_TOP_G	integer := 7
NUM_VC_EN_G	integer range 1 to 4 := 4
TX_ENABLE_G	boolean := true
RX_ENABLE_G	boolean := true

Signals
extRst	sl
pgpClk	sl
pgpRst	sl
stableClk	sl
pgpTxIn	Pgp2bTxInType
pgpTxOut	Pgp2bTxOutType
pgpRxIn	Pgp2bRxInType
pgpRxOut	Pgp2bRxOutType
pgpTxMasters	AxiStreamMasterArray ( 3 downto 0 )
pgpTxSlaves	AxiStreamSlaveArray ( 3 downto 0 )
pgpRxMasters	AxiStreamMasterArray ( 3 downto 0 )
pgpRxCtrl	AxiStreamCtrlArray ( 3 downto 0 )
gtClkP	sl
gtClkN	sl
gtTxP	sl
gtTxN	sl
gtRxP	sl
gtRxN	sl
txPreCursor	slv ( 4 downto 0 ) := ( others = > ' 0 ' )
txPostCursor	slv ( 4 downto 0 ) := ( others = > ' 0 ' )
txDiffCtrl	slv ( 3 downto 0 ) := " 1000 "
axilClk	sl := ' 0 '
axilRst	sl := ' 0 '
axilReadMaster	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	AxiLiteReadSlaveType
axilWriteMaster	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	AxiLiteWriteSlaveType

Instantiations
u_pgp2bgtx7varlatwrapper	Pgp2bGtx7VarLatWrapper <Entity Pgp2bGtx7VarLatWrapper>

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The documentation for this design unit was generated from the following file:

• protocols/pgp/pgp2b/gtx7/tb/Pgp2bGtx7VarLatWrapperTb.vhd