Pgp2bGtx7Fixedlat Entity Reference

Inheritance diagram for Pgp2bGtx7Fixedlat:

Collaboration diagram for Pgp2bGtx7Fixedlat:

Entities
Pgp2bGtx7Fixedlat.rtl	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
Pgp2bPkg	Package <Pgp2bPkg>
AxiStreamPkg	Package <AxiStreamPkg>
AxiLitePkg	Package <AxiLitePkg>
vcomponents

Generics
TPD_G	time := 1 ns
COMMON_CLK_G	boolean := false
SIM_GTRESET_SPEEDUP_G	string := " FALSE "
SIM_VERSION_G	string := " 4.0 "
SIMULATION_G	boolean := false
STABLE_CLOCK_PERIOD_G	real := 8 . 0E - 9
CPLL_REFCLK_SEL_G	bit_vector := " 001 "
CPLL_FBDIV_G	integer := 4
CPLL_FBDIV_45_G	integer := 5
CPLL_REFCLK_DIV_G	integer := 1
RXOUT_DIV_G	integer := 2
TXOUT_DIV_G	integer := 2
RX_CLK25_DIV_G	integer := 5
TX_CLK25_DIV_G	integer := 5
PMA_RSV_G	bit_vector := x " 00018480 "
RX_OS_CFG_G	bit_vector := " 0000010000000 "
RXCDR_CFG_G	bit_vector := x " 03000023FF40200020 "
RXDFEXYDEN_G	sl := ' 0 '
RX_DFE_KL_CFG2_G	bit_vector := x " 3008E56A "
RX_EQUALIZER_G	string := " DFE "
TX_BUF_EN_G	boolean := false
TX_OUTCLK_SRC_G	string := " PLLREFCLK "
TX_PHASE_ALIGN_G	string := " MANUAL "
TX_PLL_G	string := " QPLL "
RX_PLL_G	string := " CPLL "
VC_INTERLEAVE_G	integer := 0
PAYLOAD_CNT_TOP_G	integer := 7
NUM_VC_EN_G	integer range 1 to 4 := 4
TX_POLARITY_G	sl := ' 0 '
RX_POLARITY_G	sl := ' 0 '
TX_ENABLE_G	boolean := true
RX_ENABLE_G	boolean := true

Ports
stableClk	in	sl
gtCPllRefClk	in	sl := ' 0 '
gtCPllLock	out	sl
gtQPllRefClk	in	sl := ' 0 '
gtQPllClk	in	sl := ' 0 '
gtQPllLock	in	sl := ' 0 '
gtQPllRefClkLost	in	sl := ' 0 '
gtQPllReset	out	sl
gtRxRefClkBufg	in	sl
gtTxOutClk	out	sl
gtRxN	in	sl
gtRxP	in	sl
gtTxN	out	sl
gtTxP	out	sl
pgpTxReset	in	sl
pgpTxClk	in	sl
pgpTxMmcmReset	out	sl := ' 0 '
pgpTxMmcmLocked	in	sl := ' 1 '
pgpRxReset	in	sl
pgpRxRecClk	out	sl
pgpRxRecClkRst	out	sl
pgpRxClk	in	sl
pgpRxMmcmReset	out	sl
pgpRxMmcmLocked	in	sl := ' 1 '
pgpRxIn	in	Pgp2bRxInType
pgpRxOut	out	Pgp2bRxOutType
pgpTxIn	in	Pgp2bTxInType
pgpTxOut	out	Pgp2bTxOutType
pgpTxMasters	in	AxiStreamMasterArray ( 3 downto 0 ) := ( others = > AXI_STREAM_MASTER_INIT_C )
pgpTxSlaves	out	AxiStreamSlaveArray ( 3 downto 0 )
pgpRxMasters	out	AxiStreamMasterArray ( 3 downto 0 )
pgpRxMasterMuxed	out	AxiStreamMasterType
pgpRxCtrl	in	AxiStreamCtrlArray ( 3 downto 0 )
txPreCursor	in	slv ( 4 downto 0 ) := ( others = > ' 0 ' )
txPostCursor	in	slv ( 4 downto 0 ) := ( others = > ' 0 ' )
txDiffCtrl	in	slv ( 3 downto 0 ) := " 1000 "
axilClk	in	sl := ' 0 '
axilRst	in	sl := ' 0 '
axilReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	out	AxiLiteWriteSlaveType

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The documentation for this design unit was generated from the following file:

• protocols/pgp/pgp2b/gtx7/rtl/Pgp2bGtx7FixedLat.vhd