Pgp2bGtp7VarLat Entity Reference

Inheritance diagram for Pgp2bGtp7VarLat:

Collaboration diagram for Pgp2bGtp7VarLat:

Entities
Pgp2bGtp7VarLat.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
Pgp2bPkg	Package <Pgp2bPkg>
AxiStreamPkg	Package <AxiStreamPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
TPD_G	time := 1 ns
COMMON_CLK_G	boolean := false
SIM_GTRESET_SPEEDUP_G	string := " FALSE "
SIM_VERSION_G	string := " 2.0 "
STABLE_CLOCK_PERIOD_G	real := 4 . 0E - 9
RXOUT_DIV_G	integer := 2
TXOUT_DIV_G	integer := 2
RX_CLK25_DIV_G	integer := 7
TX_CLK25_DIV_G	integer := 7
PMA_RSV_G	bit_vector := x " 00000333 "
RX_OS_CFG_G	bit_vector := " 0001111110000 "
RXCDR_CFG_G	bit_vector := x " 0000107FE206001041010 "
RXLPM_INCM_CFG_G	bit := ' 1 '
RXLPM_IPCM_CFG_G	bit := ' 0 '
DYNAMIC_QPLL_G	boolean := false
TX_PLL_G	string := " PLL0 "
RX_PLL_G	string := " PLL1 "
TX_BUF_EN_G	boolean := true
TX_OUTCLK_SRC_G	string := " OUTCLKPMA "
TX_DLY_BYPASS_G	sl := ' 1 '
TX_PHASE_ALIGN_G	string := " NONE "
TX_BUF_ADDR_MODE_G	string := " FULL "
VC_INTERLEAVE_G	integer := 0
PAYLOAD_CNT_TOP_G	integer := 7
NUM_VC_EN_G	integer range 1 to 4 := 4
TX_POLARITY_G	sl := ' 0 '
RX_POLARITY_G	sl := ' 0 '
TX_ENABLE_G	boolean := true
RX_ENABLE_G	boolean := true

Ports
stableClk	in	sl
qPllRxSelect	in	slv ( 1 downto 0 ) := " 00 "
qPllTxSelect	in	slv ( 1 downto 0 ) := " 00 "
gtQPllOutRefClk	in	slv ( 1 downto 0 )
gtQPllOutClk	in	slv ( 1 downto 0 )
gtQPllLock	in	slv ( 1 downto 0 )
gtQPllRefClkLost	in	slv ( 1 downto 0 )
gtQPllReset	out	slv ( 1 downto 0 )
gtTxP	out	sl
gtTxN	out	sl
gtRxP	in	sl
gtRxN	in	sl
pgpTxReset	in	sl
pgpTxRecClk	out	sl
pgpTxClk	in	sl
pgpTxMmcmReset	out	sl
pgpTxMmcmLocked	in	sl := ' 1 '
pgpRxReset	in	sl
pgpRxRecClk	out	sl
pgpRxClk	in	sl
pgpRxMmcmReset	out	sl
pgpRxMmcmLocked	in	sl := ' 1 '
pgpRxIn	in	Pgp2bRxInType
pgpRxOut	out	Pgp2bRxOutType
pgpTxIn	in	Pgp2bTxInType
pgpTxOut	out	Pgp2bTxOutType
pgpTxMasters	in	AxiStreamMasterArray ( 3 downto 0 ) := ( others = > AXI_STREAM_MASTER_INIT_C )
pgpTxSlaves	out	AxiStreamSlaveArray ( 3 downto 0 )
pgpRxMasters	out	AxiStreamMasterArray ( 3 downto 0 )
pgpRxMasterMuxed	out	AxiStreamMasterType
pgpRxCtrl	in	AxiStreamCtrlArray ( 3 downto 0 )
txPreCursor	in	slv ( 4 downto 0 ) := ( others = > ' 0 ' )
txPostCursor	in	slv ( 4 downto 0 ) := ( others = > ' 0 ' )
txDiffCtrl	in	slv ( 3 downto 0 ) := " 1000 "
drpOverride	in	sl := ' 0 '
axilClk	in	sl := ' 0 '
axilRst	in	sl := ' 0 '
axilReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	out	AxiLiteWriteSlaveType

---

The documentation for this design unit was generated from the following file:

• protocols/pgp/pgp2b/gtp7/rtl/Pgp2bGtp7VarLat.vhd