Pgp2bGth7FixedLatWrapper Entity Reference

Inheritance diagram for Pgp2bGth7FixedLatWrapper:

Collaboration diagram for Pgp2bGth7FixedLatWrapper:

Entities
Pgp2bGth7FixedLatWrapper.rtl	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
numeric_std
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
Pgp2bPkg	Package <Pgp2bPkg>
AxiLitePkg	Package <AxiLitePkg>
vcomponents

Generics
MASTER_SEL_G	boolean := true
RX_CLK_SEL_G	boolean := true
VC_INTERLEAVE_G	integer := 0
PAYLOAD_CNT_TOP_G	integer := 7
NUM_VC_EN_G	integer range 1 to 4 := 4
TX_POLARITY_G	sl := ' 0 '
RX_POLARITY_G	sl := ' 0 '
TX_ENABLE_G	boolean := true
RX_ENABLE_G	boolean := true
QPLL_FBDIV_G	bit_vector := " 0100100000 "
QPLL_FBDIV_RATIO_G	bit := ' 1 '
QPLL_REFCLK_DIV_G	integer := 1
CPLL_FBDIV_G	integer range 1 to 5 := 4
CPLL_FBDIV_45_G	integer range 4 to 5 := 5
CPLL_REFCLK_DIV_G	integer range 1 to 2 := 1
MMCM_CLKIN_PERIOD_G	real := 8 . 000
MMCM_CLKFBOUT_MULT_G	real := 8 . 000
MMCM_GTCLK_DIVIDE_G	real := 8 . 000
MMCM_TXCLK_DIVIDE_G	natural := 8
RXOUT_DIV_G	integer := 2
TXOUT_DIV_G	integer := 4
RX_CLK25_DIV_G	integer := 5
TX_CLK25_DIV_G	integer := 5
RX_OS_CFG_G	bit_vector := " 0000010000000 "
RXCDR_CFG_G	bit_vector := x " 0002007FE1000C2200018 "
RXDFEXYDEN_G	sl := ' 0 '
TX_PLL_G	string := " QPLL "
RX_PLL_G	string := " CPLL "

Ports
extRst	in	sl
txPllLock	out	sl
rxPllLock	out	sl
txClk	out	sl
rxClk	out	sl
stableClk	out	sl
pgpRxIn	in	Pgp2bRxInType
pgpRxOut	out	Pgp2bRxOutType
pgpTxIn	in	Pgp2bTxInType
pgpTxOut	out	Pgp2bTxOutType
pgpTxMasters	in	AxiStreamMasterArray ( 3 downto 0 )
pgpTxSlaves	out	AxiStreamSlaveArray ( 3 downto 0 )
pgpRxMasters	out	AxiStreamMasterArray ( 3 downto 0 )
pgpRxMasterMuxed	out	AxiStreamMasterType
pgpRxCtrl	in	AxiStreamCtrlArray ( 3 downto 0 )
gtClkP	in	sl
gtClkN	in	sl
gtTxP	out	sl
gtTxN	out	sl
gtRxP	in	sl
gtRxN	in	sl
txPreCursor	in	slv ( 4 downto 0 ) := ( others = > ' 0 ' )
txPostCursor	in	slv ( 4 downto 0 ) := ( others = > ' 0 ' )
txDiffCtrl	in	slv ( 3 downto 0 ) := " 1000 "
axilClk	in	sl := ' 0 '
axilRst	in	sl := ' 0 '
axilReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	out	AxiLiteWriteSlaveType

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The documentation for this design unit was generated from the following file:

• protocols/pgp/pgp2b/gth7/rtl/Pgp2bGth7FixedLatWrapper.vhd