Mux.rtl Architecture Reference

Architecture >> Mux::rtl

Processes
comb	( din , r , rst , sel )
seq	( clk , rst )
comb	( din , r , rst , sel )
seq	( clk , rst )

Constants
REG_INIT_C	RegType := ( sel = > ( others = > ' 0 ' ) , din = > ( others = > ' 0 ' ) , dout = > ' 0 ' )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following files:

• base/general/rtl/Mux.vhd
• build/SRC_VHDL/surf/Mux.vhd