Architecture >> MasterRamIpIntegrator::mapping

Attributes
X_INTERFACE_INFO	string
X_INTERFACE_PARAMETER	string
X_INTERFACE_INFO	signal is " xilinx.com : interface : bram : 1.0 " & INTERFACENAME& " CLK "
X_INTERFACE_INFO	signal is " xilinx.com : interface : bram : 1.0 " & INTERFACENAME& " EN "
X_INTERFACE_INFO	signal is " xilinx.com : interface : bram : 1.0 " & INTERFACENAME& " WE "
X_INTERFACE_INFO	signal is " xilinx.com : interface : bram : 1.0 " & INTERFACENAME& " RST "
X_INTERFACE_INFO	signal is " xilinx.com : interface : bram : 1.0 " & INTERFACENAME& " ADDR "
X_INTERFACE_INFO	signal is " xilinx.com : interface : bram : 1.0 " & INTERFACENAME& " DIN "
X_INTERFACE_INFO	signal is " xilinx.com : interface : bram : 1.0 " & INTERFACENAME& " DOUT "
X_INTERFACE_PARAMETER	signal is " XIL_INTERFACENAME " & INTERFACENAME& " , " & " MEM_SIZE " & integer ' image ( 2 ** ADDR_WIDTH ) & " , " & " MEM_WIDTH " & integer ' image ( DATA_WIDTH ) & " , " & " MEM_ECC NONE , " & " MASTER_TYPE OTHER , " & " READ_LATENCY " & integer ' image ( READ_LATENCY )

The documentation for this design unit was generated from the following file:

Attributes