MasterRamIpIntegrator Entity Reference

Entities
MasterRamIpIntegrator.mapping	architecture

Libraries
ieee

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned

Generics
INTERFACENAME	string := " M_RAM "
READ_LATENCY	natural range 0 to 3 := 1
ADDR_WIDTH	positive := 5
DATA_WIDTH	positive := 32

Ports
M_RAM_CLK	out	std_logic
M_RAM_EN	out	std_logic
M_RAM_WE	out	std_logic_vector ( ( DATA_WIDTH/ 8 ) - 1 downto 0 )
M_RAM_RST	out	std_logic
M_RAM_ADDR	out	std_logic_vector ( ADDR_WIDTH- 1 downto 0 )
M_RAM_DIN	out	std_logic_vector ( DATA_WIDTH- 1 downto 0 )
M_RAM_DOUT	in	std_logic_vector ( DATA_WIDTH- 1 downto 0 ) := ( others = > ' 0 ' )
clk	in	std_logic := ' 0 '
en	in	std_logic := ' 1 '
we	in	std_logic_vector ( ( DATA_WIDTH/ 8 ) - 1 downto 0 ) := ( others = > ' 0 ' )
rst	in	std_logic := ' 0 '
addr	in	std_logic_vector ( ADDR_WIDTH- 1 downto 0 ) := ( others = > ' 0 ' )
din	in	std_logic_vector ( DATA_WIDTH- 1 downto 0 ) := ( others = > ' 0 ' )
dout	out	std_logic_vector ( DATA_WIDTH- 1 downto 0 )

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The documentation for this design unit was generated from the following file:

• base/general/ip_integrator/MasterRamIpIntegrator.vhd