Architecture >> MasterAxiIpIntegrator::mapping

Signals
M_AXI_ReadMaster	AxiReadMasterType := AXI_READ_MASTER_INIT_C
M_AXI_ReadSlave	AxiReadSlaveType := AXI_READ_SLAVE_INIT_C
M_AXI_WriteMaster	AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C
M_AXI_WriteSlave	AxiWriteSlaveType := AXI_WRITE_SLAVE_INIT_C

Attributes
X_INTERFACE_INFO	string
X_INTERFACE_PARAMETER	string
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " AWID "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " AWADDR "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " AWLEN "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " AWSIZE "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " AWBURST "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " AWLOCK "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " AWCACHE "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " AWPROT "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " AWREGION "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " AWQOS "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " AWVALID "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " AWREADY "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " WID "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " WDATA "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " WSTRB "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " WLAST "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " WVALID "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " WREADY "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " BID "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " BRESP "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " BVALID "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " BREADY "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " ARID "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " ARADDR "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " ARLEN "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " ARSIZE "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " ARBURST "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " ARLOCK "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " ARCACHE "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " ARPROT "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " ARREGION "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " ARQOS "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " ARVALID "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " ARREADY "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " RID "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " RDATA "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " RRESP "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " RLAST "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " RVALID "
X_INTERFACE_INFO	signal is " xilinx.com : interface : aximm : 1.0 " & INTERFACENAME& " RREADY "
X_INTERFACE_PARAMETER	signal is " XIL_INTERFACENAME " & INTERFACENAME& " , " & " PROTOCOL AXI4 , " & " MAX_BURST_LENGTH " & integer ' image ( MAX_BURST_LENGTH ) & " , " & " NUM_WRITE_OUTSTANDING " & integer ' image ( NUM_WRITE_OUTSTANDING ) & " , " & " NUM_READ_OUTSTANDING " & integer ' image ( NUM_READ_OUTSTANDING ) & " , " & " SUPPORTS_NARROW_BURST " & integer ' image ( SUPPORTS_NARROW_BURST ) & " , " & " ADDR_WIDTH " & integer ' image ( ADDR_WIDTH ) & " , " & " ID_WIDTH " & integer ' image ( ID_WIDTH ) & " , " & " DATA_WIDTH " & integer ' image ( DATA_WIDTH ) & " , " & " HAS_BURST " & integer ' image ( HAS_BURST ) & " , " & " HAS_CACHE " & integer ' image ( HAS_CACHE ) & " , " & " HAS_LOCK " & integer ' image ( HAS_LOCK ) & " , " & " HAS_PROT " & integer ' image ( HAS_PROT ) & " , " & " HAS_QOS " & integer ' image ( HAS_QOS ) & " , " & " HAS_REGION " & integer ' image ( HAS_REGION ) & " , " & " HAS_WSTRB " & integer ' image ( HAS_WSTRB ) & " , " & " HAS_BRESP " & integer ' image ( HAS_BRESP ) & " , " & " HAS_RRESP " & integer ' image ( HAS_RRESP )
X_INTERFACE_INFO	signal is " xilinx.com : signal : reset : 1.0 RST. " & INTERFACENAME& " _ARESETN RST "
X_INTERFACE_PARAMETER	signal is " XIL_INTERFACENAME RST. " & INTERFACENAME& " _ARESETN , " & " POLARITY ACTIVE_LOW "
X_INTERFACE_INFO	signal is " xilinx.com : signal : clock : 1.0 CLK. " & INTERFACENAME& " _ACLK CLK "
X_INTERFACE_PARAMETER	signal is " XIL_INTERFACENAME CLK. " & INTERFACENAME& " _ACLK , " & " ASSOCIATED_BUSIF " & INTERFACENAME& " , " & " ASSOCIATED_RESET " & INTERFACENAME& " _ARESETN "

Instantiations
u_rstsync	RstSync <Entity RstSync>

The documentation for this design unit was generated from the following file:

axi/axi4/ip_integrator/MasterAxiIpIntegrator.vhd

Signals

Attributes

Instantiations