LutRam.rtl Architecture Reference

Architecture >> LutRam::rtl

Processes
PROCESS_40	( clka )
PROCESS_41	( clka )
PROCESS_42	( clka , rsta )
PROCESS_43	( clka , rsta )
PROCESS_44	( clka , rsta )
PROCESS_45	( clkb , rstb )
PROCESS_46	( clkc , rstc )
PROCESS_47	( clkd , rstd )
PROCESS_48	( clke , rste )
PROCESS_49	( clkf , rstf )
PROCESS_50	( clkg , rstg )
PROCESS_51	( clkh , rsth )
PROCESS_130	( clka )
PROCESS_131	( clka )
PROCESS_132	( clka , rsta )
PROCESS_133	( clka , rsta )
PROCESS_134	( clka , rsta )
PROCESS_135	( clkb , rstb )
PROCESS_136	( clkc , rstc )
PROCESS_137	( clkd , rstd )
PROCESS_138	( clke , rste )
PROCESS_139	( clkf , rstf )
PROCESS_140	( clkg , rstg )
PROCESS_141	( clkh , rsth )

Constants
NUM_BYTES_C	natural := wordCount ( DATA_WIDTH_G , BYTE_WIDTH_G )
FULL_DATA_WIDTH_C	natural := NUM_BYTES_C* BYTE_WIDTH_G
INIT_C	slv ( DATA_WIDTH_G- 1 downto 0 ) := ite ( INIT_G = " 0 " , slvZero ( DATA_WIDTH_G ) , INIT_G )

Types
MemType	( ( 2 ** ADDR_WIDTH_G ) - 1 downto 0 ) slv ( DATA_WIDTH_G- 1 downto 0 )

Signals
mem	MemType := ( others = > INIT_C )
weaByteInt	slv ( weaByte )

Attributes
ram_style	string
ram_style	signal is " distributed "
ram_extract	string
ram_extract	signal is " TRUE "
syn_ramstyle	string
syn_ramstyle	signal is " distributed "
syn_keep	string
syn_keep	signal is " TRUE "

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The documentation for this design unit was generated from the following files:

• base/ram/inferred/LutRam.vhd
• build/SRC_VHDL/surf/LutRam.vhd