SURF
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Generics | Libraries | Ports | Use Clauses
LutRam Entity Reference
+ Inheritance diagram for LutRam:

Entities

LutRam.rtl  architecture
 

Libraries

ieee 
surf 

Use Clauses

std_logic_1164 
std_logic_arith 
std_logic_unsigned 
StdRtlPkg  Package <StdRtlPkg>

Generics

TPD_G  time := 1 ns
RST_POLARITY_G  sl := ' 1 '
RST_ASYNC_G  boolean := false
REG_EN_G  boolean := true
MODE_G  string := " no-change "
BYTE_WR_EN_G  boolean := false
DATA_WIDTH_G  positive := 16
BYTE_WIDTH_G  positive := 8
ADDR_WIDTH_G  positive := 4
NUM_PORTS_G  positive
INIT_G  slv := " 0 "

Ports

clka   in   sl := ' 0 '
en_a   in   sl := ' 1 '
wea   in   sl := ' 0 '
weaByte   in   slv ( wordCount ( DATA_WIDTH_G , BYTE_WIDTH_G ) - 1 downto 0 ) := ( others = > ' 0 ' )
rsta   in   sl := not ( RST_POLARITY_G )
addra   in   slv ( ADDR_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
dina   in   slv ( DATA_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
douta   out   slv ( DATA_WIDTH_G- 1 downto 0 )
clkb   in   sl := ' 0 '
en_b   in   sl := ' 1 '
rstb   in   sl := not ( RST_POLARITY_G )
addrb   in   slv ( ADDR_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
doutb   out   slv ( DATA_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
en_c   in   sl := ' 1 '
clkc   in   sl := ' 0 '
rstc   in   sl := not ( RST_POLARITY_G )
addrc   in   slv ( ADDR_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
doutc   out   slv ( DATA_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
en_d   in   sl := ' 1 '
clkd   in   sl := ' 0 '
rstd   in   sl := not ( RST_POLARITY_G )
addrd   in   slv ( ADDR_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
doutd   out   slv ( DATA_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
en_e   in   sl := ' 1 '
clke   in   sl := ' 0 '
rste   in   sl := not ( RST_POLARITY_G )
addre   in   slv ( ADDR_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
doute   out   slv ( DATA_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
en_f   in   sl := ' 1 '
clkf   in   sl := ' 0 '
rstf   in   sl := not ( RST_POLARITY_G )
addrf   in   slv ( ADDR_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
doutf   out   slv ( DATA_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
en_g   in   sl := ' 1 '
clkg   in   sl := ' 0 '
rstg   in   sl := not ( RST_POLARITY_G )
addrg   in   slv ( ADDR_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
doutg   out   slv ( DATA_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
en_h   in   sl := ' 1 '
clkh   in   sl := ' 0 '
rsth   in   sl := not ( RST_POLARITY_G )
addrh   in   slv ( ADDR_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
douth   out   slv ( DATA_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
The documentation for this design unit was generated from the following files: