JesdIlasGen.rtl Architecture Reference

Architecture >> JesdIlasGen::rtl

Processes
comb	( enable_i , ilas_i , lmfc_i , r , rst )
seq	( clk )
comb	( enable_i , ilas_i , lmfc_i , r , rst )
seq	( clk )

Constants
REG_INIT_C	RegType := ( lmfcD1 = > ' 0 ' , lmfcD2 = > ' 0 ' )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/JesdIlasGen.vhd
• protocols/jesd204b/rtl/JesdIlasGen.vhd