JesdAlignFrRepCh.rtl Architecture Reference

Architecture >> JesdAlignFrRepCh::rtl

Processes
comb	( alignFrame_i , chariskRx_i , dataRx_i , dataValid_i , r , replEnable_i , rst , scrEnable_i )
seq	( clk )
comb	( alignFrame_i , chariskRx_i , dataRx_i , dataValid_i , r , replEnable_i , rst , scrEnable_i )
seq	( clk )

Constants
SAMPLES_IN_WORD_C	positive := ( GT_WORD_SIZE_C/ F_G )
REG_INIT_C	RegType := ( dataRxD1 = > ( others = > ' 0 ' ) , chariskRxD1 = > ( others = > ' 0 ' ) , dataAlignedD1 = > ( others = > ' 0 ' ) , charAlignedD1 = > ( others = > ' 0 ' ) , scrData = > ( others = > ' 0 ' ) , lfsr = > ( others = > ' 0 ' ) , descrData = > ( others = > ' 0 ' ) , scrDataValid = > ' 0 ' , sampleData = > ( others = > ' 0 ' ) , descrDataValid = > ' 0 ' , dataValid = > ' 0 ' , position = > intToSlv ( 1 , GT_WORD_SIZE_C ) )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/JesdAlignFrRepCh.vhd
• protocols/jesd204b/rtl/JesdAlignFrRepCh.vhd