InputBufferReg.rtl Architecture Reference

Architecture >> InputBufferReg::rtl

Signals
inputSig	sl
CB	sl

Instantiations
u_ibufds	ibuf
u_ibufds	ibufds
u_iddr	iddr
u_ibufds	ibuf
u_ibufds	ibufds
u_iddr	iddre1

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The documentation for this design unit was generated from the following files:

• xilinx/7Series/general/rtl/InputBufferReg.vhd
• xilinx/UltraScale/general/rtl/InputBufferReg.vhd