Architecture >> IirSimple::rtl

Constants
IIR_DELAY_C	integer := ILEAVE_CHAN_G- 1
IIR_DELAY_STYLE_C	string := ite ( IIR_DELAY_C> BRAM_THRESH_G , " block " , " srl_reg " )
TOT_LATENCY_C	integer := 1 + ite ( REG_IN_G , 1 , 0 ) + ite ( REG_OUT_G , 1 , 0 )
INT_OVERFLOW_STYLE_C	fixed_overflow_style_type := fixed_wrap
INT_ROUNDING_STYLE_C	fixed_round_style_type := fixed_truncate
REG_INIT_C	RegType := ( din = > ( others = > ' 0 ' ) , dout = > ( others = > ' 0 ' ) )

Signals
r	RegType := REG_INIT_C
rin	RegType
dinInt	sfixed ( din )
doutInt	sfixed ( dout )
filtOut	sfixed ( dout ' high downto dout ' low- IIR_SHIFT_G )
filtDly	sfixed ( dout ' high downto dout ' low- IIR_SHIFT_G )
userDelayIn	slv ( userIn ' length downto 0 )
userDelayOut	slv ( userIn ' length downto 0 )
shiftInA	sfixed ( din ' high- IIR_SHIFT_G downto din ' low- IIR_SHIFT_G )
shiftInB	sfixed ( filtOut ' high- IIR_SHIFT_G downto filtOut ' low- IIR_SHIFT_G )

Records
RegType

Instantiations
u_user_delay	SlvFixedDelay <Entity SlvFixedDelay>
u_accum_delay	sfixedDelay <Entity sfixedDelay>
u_add_sub	add3 <Entity add3>

The documentation for this design unit was generated from the following file:

Processes

Constants