IirSimpleTb.test Architecture Reference

Architecture >> IirSimpleTb::test

Functions
real	randNum ( min_val: in real , max_val: in real )	[ impure ]

Processes
comb	( dout , r , rst , userOut , validOut )
seq	( clk )
PROCESS_210	( failed , passed )

Constants
TPD_C	time := 1 ns
CLK_PERIOD_C	time := 10 ns
ERROR_TOL_C	real := 0 . 0001
RUN_CNT_C	integer := 10000
IIR_SHIFT_C	integer := 4
ILEAVE_C	integer := 7
FILT_A_C	real := 2 ** ( - real ( IIR_SHIFT_C ) )
REG_INIT_C	RegType := ( cnt = > 0 , passed = > ' 0 ' , failed = > ' 0 ' , halt = > ' 0 ' , dinR = > 0 . 0 , doutR = > 0 . 0 , din = > ( others = > ' 0 ' ) , dout = > ( others = > ' 0 ' ) , validIn = > ' 0 ' , validOut = > ' 0 ' , userIn = > ( others = > ' 0 ' ) , userOut = > ( others = > ' 0 ' ) , expected = > 0 . 0 , err = > 0 . 0 , maxError = > 0 . 0 , state = > INIT_S )

Types
StateType	( INIT_S , RUNNING_S , FAILED_S , PASSED_S )

Signals
clk	std_logic := ' 0 '
rst	std_logic := ' 1 '
r	RegType := REG_INIT_C
rin	RegType
dout	sfixed ( r.dout ' range )
validOut	sl
userOut	slv ( r.userOut ' range )
passed	sl := ' 0 '
failed	sl := ' 0 '

Records
RegType

Instantiations
u_clkrst	ClkRst <Entity ClkRst>
u_dut	IirSimple <Entity IirSimple>

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The documentation for this design unit was generated from the following file:

• dsp/tb/IirSimpleTb.vhd