IgmpV2Engine.rtl Architecture Reference

Architecture >> IgmpV2Engine::rtl

Processes
comb	( ibIgmpMaster , igmpIp , localIp , obIgmpSlave , r , rst )
seq	( clk )

Constants
TIMER_100MS_C	natural := getTimeRatio ( CLK_FREQ_G , 10 . 0 )
REG_INIT_C	RegType := ( txCnt = > 0 , cnt = > 0 , sendReport = > ( others = > ' 1 ' ) , rndCnt = > ( others = > ' 0 ' ) , timer = > ( others = > ' 1 ' ) , obIgmpMaster = > AXI_STREAM_MASTER_INIT_C , rxState = > RX_IDLE_S , txState = > TX_IDLE_S )

Types
RxStateType	( RX_IDLE_S , RX_MSG_S )
TxStateType	( TX_IDLE_S , TX_MSG_S )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following file:

• ethernet/IpV4Engine/rtl/IgmpV2Engine.vhd