IgmpV2Engine Entity Reference

Inheritance diagram for IgmpV2Engine:

Entities
IgmpV2Engine.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
SsiPkg	Package <SsiPkg>
EthMacPkg	Package <EthMacPkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
IGMP_GRP_SIZE	positive := 1
CLK_FREQ_G	real := 156 . 25E + 06

Ports
localIp	in	slv ( 31 downto 0 )
igmpIp	in	Slv32Array ( IGMP_GRP_SIZE- 1 downto 0 )
ibIgmpMaster	in	AxiStreamMasterType
ibIgmpSlave	out	AxiStreamSlaveType
obIgmpMaster	out	AxiStreamMasterType
obIgmpSlave	in	AxiStreamSlaveType
clk	in	sl
rst	in	sl

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The documentation for this design unit was generated from the following file:

• ethernet/IpV4Engine/rtl/IgmpV2Engine.vhd