I2cRegTb.tb Architecture Reference

Architecture >> I2cRegTb::tb

Processes
sim
sim

Constants
TPD_C	time := 1 ns

Signals
masterClk	sl
masterRst	sl
slaveClk	slv ( 15 downto 0 )
slaveRst	slv ( 15 downto 0 )
regIn	i2cRegMasterInType
regOut	i2cRegMasterOutType
i2ci	i2c_in_type
i2co	i2c_out_type
i2cSda	sl
i2cScl	sl

Instantiations
clkrst_master	ClkRst <Entity ClkRst>
i2cregmaster_1	I2cRegMaster <Entity I2cRegMaster>
clkrst_slave	ClkRst <Entity ClkRst>
i2cramslave_1	I2cRamSlave <Entity I2cRamSlave>
clkrst_master	ClkRst <Entity ClkRst>
i2cregmaster_1	I2cRegMaster <Entity I2cRegMaster>
clkrst_slave	ClkRst <Entity ClkRst>
i2cramslave_1	I2cRamSlave <Entity I2cRamSlave>

---

The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/I2cRegTb.vhd
• protocols/i2c/sim/I2cRegTb.vhd