I2cRamSlave.rtl Architecture Reference

Architecture >> I2cRamSlave::rtl

Processes
ram_proc	( clk )
ram_proc	( clk )

Types
RamType	( 0 to 2 ** ( 8 * ADDR_SIZE_G ) - 1 ) slv ( 8 * DATA_SIZE_G- 1 downto 0 )

Signals
i2ci	i2c_in_type
i2co	i2c_out_type
ram	RamType
addr	slv ( 8 * ADDR_SIZE_G- 1 downto 0 )
wrEn	sl
wrData	slv ( 8 * DATA_SIZE_G- 1 downto 0 )
rdEn	sl
rdData	slv ( 8 * DATA_SIZE_G- 1 downto 0 )

Instantiations
i2cregslave_1	I2cRegSlave <Entity I2cRegSlave>
i2cregslave_1	I2cRegSlave <Entity I2cRegSlave>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/I2cRamSlave.vhd
• protocols/i2c/sim/I2cRamSlave.vhd