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HammingEccTb.sim Architecture Reference
Architecture >> HammingEccTb::sim

Processes

comb  ( obData , obErrDbit , obErrSbit , obValid , r , rst )
seq  ( clk )
PROCESS_112  ( failed , passed )
comb  ( obData , obErrDbit , obErrSbit , obValid , r , rst )
seq  ( clk )
PROCESS_243  ( failed , passed )

Constants

CLK_PERIOD_C  time := 4 ns
TPD_G  time := CLK_PERIOD_C/ 4
DATA_WIDTH_C  positive := 8
ENC_WIDTH_C  positive := hammingEccDataWidth ( DATA_WIDTH_C )
k  positive := DATA_WIDTH_C
m  positive := hammingEccPartiyWidth ( k )
n  positive := hammingEccDataWidth ( k )
REG_INIT_C  RegType := ( passed = > ' 0 ' , failed = > ' 0 ' , ibValid = > ' 0 ' , ibData = > ( others = > ' 0 ' ) , bitErrorMask = > ( others = > ' 0 ' ) , state = > LOAD_S )

Types

StateType  ( LOAD_S , WAIT_S , FAILED_S , PASSED_S )

Signals

r  RegType := REG_INIT_C
rin  RegType
clk  sl := ' 0 '
rst  sl := ' 1 '
encValid  sl := ' 0 '
encData  slv ( ENC_WIDTH_C downto 0 ) := ( others = > ' 0 ' )
encDataMask  slv ( ENC_WIDTH_C downto 0 ) := ( others = > ' 0 ' )
obValid  sl := ' 0 '
obData  slv ( DATA_WIDTH_C- 1 downto 0 ) := ( others = > ' 0 ' )
obErrSbit  sl := ' 0 '
obErrDbit  sl := ' 0 '
passed  sl := ' 0 '
failed  sl := ' 0 '

Records

RegType 

Instantiations

u_clkrst  ClkRst <Entity ClkRst>
u_encoder  HammingEccEncoder <Entity HammingEccEncoder>
u_decoder  HammingEccDecoder <Entity HammingEccDecoder>
u_clkrst  ClkRst <Entity ClkRst>
u_encoder  HammingEccEncoder <Entity HammingEccEncoder>
u_decoder  HammingEccDecoder <Entity HammingEccDecoder>

The documentation for this design unit was generated from the following files: