Gtp7AutoPhaseAligner.RTL Architecture Reference

Architecture >> Gtp7AutoPhaseAligner::RTL

Processes
PROCESS_397	( STABLE_CLOCK )
PROCESS_398	( STABLE_CLOCK )

Libraries
surf

Types
PhaseAlignFsmType	( INIT , WAIT_PHRST_DONE , COUNT_PHALIGN_DONE , PHALIGN_DONE )

Signals
phalign_state	PhaseAlignFsmType := INIT
phaligndone_prev	std_logic := ' 0 '
phaligndone_ris_edge	std_logic
count_phalign_edges	integer range 0 to 3 := 0
phaligndone_sync	std_logic := ' 0 '
dlysresetdone_sync	std_logic := ' 0 '

Instantiations
sync_phaligndone	Synchronizer <Entity Synchronizer>
sync_dlysresetdone	Synchronizer <Entity Synchronizer>

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The documentation for this design unit was generated from the following file:

• xilinx/7Series/gtp7/rtl/Gtp7AutoPhaseAligner.vhd