GthUltraScaleQuadPll.mapping Architecture Reference

Architecture >> GthUltraScaleQuadPll::mapping

Signals
gtRefClk0	slv ( 1 downto 0 )
gtRefClk1	slv ( 1 downto 0 )
gtNorthRefClk0	slv ( 1 downto 0 )
gtNorthRefClk1	slv ( 1 downto 0 )
gtSouthRefClk0	slv ( 1 downto 0 )
gtSouthRefClk1	slv ( 1 downto 0 )
gtGRefClk	slv ( 1 downto 0 )
drpEn	sl := ' 0 '
drpWe	sl := ' 0 '
drpRdy	sl := ' 0 '
drpAddr	slv ( 15 downto 0 ) := ( others = > ' 0 ' )
drpDi	slv ( 15 downto 0 ) := ( others = > ' 0 ' )
drpDo	slv ( 15 downto 0 ) := ( others = > ' 0 ' )
drpAddr	slv ( 8 downto 0 ) := ( others = > ' 0 ' )

Instantiations
gthe4_common_inst	gthe4_common
u_axilitetodrp	AxiLiteToDrp <Entity AxiLiteToDrp>
gthe3_common_inst	gthe3_common
u_axilitetodrp	AxiLiteToDrp <Entity AxiLiteToDrp>

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The documentation for this design unit was generated from the following files:

• xilinx/UltraScale+/gthUs/rtl/GthUltraScaleQuadPll.vhd
• xilinx/UltraScale/gthUs/rtl/GthUltraScaleQuadPll.vhd