Gth7RxRst.RTL Architecture Reference

Architecture >> Gth7RxRst::RTL

Processes
PROCESS_389	( STABLE_CLOCK )
PROCESS_390	( STABLE_CLOCK )
retries_recclk_monitor	( STABLE_CLOCK )
timeouts	( STABLE_CLOCK )
mmcm_lock_wait	( MMCM_LOCK , RXUSERCLK )
timeout_buffer_bypass	( RXUSERCLK )
reset_fsm	( STABLE_CLOCK )

Constants
MMCM_LOCK_CNT_MAX	integer := 1024
STARTUP_DELAY	integer := 500
WAIT_CYCLES	integer := STARTUP_DELAY/ STABLE_CLOCK_PERIOD
WAIT_MAX	integer := WAIT_CYCLES+ 10
WAIT_TIMEOUT_2ms	integer := 3000000 / STABLE_CLOCK_PERIOD
WAIT_TLOCK_MAX	integer := 100000 / STABLE_CLOCK_PERIOD
WAIT_TIMEOUT_500us	integer := 500000 / STABLE_CLOCK_PERIOD
WAIT_TIMEOUT_1us	integer := 1000 / STABLE_CLOCK_PERIOD
WAIT_TIMEOUT_100us	integer := 100000 / STABLE_CLOCK_PERIOD
WAIT_TIME_ADAPT	integer := ( 37000000 / integer ( 3 . 125 ) ) / STABLE_CLOCK_PERIOD
MAX_RETRIES	integer := 2 ** RETRY_COUNTER_BITWIDTH- 1
MAX_WAIT_BYPASS	integer := 5000

Types
RxRstFsmType	( INIT , ASSERT_ALL_RESETS , RELEASE_PLL_RESET , VERIFY_RECCLK_STABLE , RELEASE_MMCM_RESET , WAIT_RESET_DONE , DO_PHASE_ALIGNMENT , MONITOR_DATA_VALID , FSM_DONE )

Signals
rx_state	RxRstFsmType := INIT
soft_reset_sync	std_logic
soft_reset_rise	std_logic
soft_reset_fall	std_logic
init_wait_count	integer range 0 to WAIT_MAX := 0
init_wait_done	std_logic := ' 0 '
pll_reset_asserted	std_logic := ' 0 '
rx_fsm_reset_done_int	std_logic := ' 0 '
rx_fsm_reset_done_int_s3	std_logic := ' 0 '
rxresetdone_s3	std_logic := ' 0 '
retry_counter_int	integer range 0 to MAX_RETRIES := 0
time_out_counter	integer range 0 to WAIT_TIMEOUT_2ms := 0
recclk_mon_restart_count	integer range 0 to 3 := 0
recclk_mon_count_reset	std_logic := ' 0 '
reset_time_out	std_logic := ' 0 '
time_out_2ms	std_logic := ' 0 '
time_tlock_max	std_logic := ' 0 '
time_out_500us	std_logic := ' 0 '
time_out_1us	std_logic := ' 0 '
time_out_100us	std_logic := ' 0 '
check_tlock_max	std_logic := ' 0 '
mmcm_lock_count	integer range 0 to MMCM_LOCK_CNT_MAX- 1 := 0
mmcm_lock_int	std_logic := ' 0 '
mmcm_lock_reclocked	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
run_phase_alignment_int	std_logic := ' 0 '
run_phase_alignment_int_s3	std_logic := ' 0 '
wait_bypass_count	integer range 0 to MAX_WAIT_BYPASS- 1
time_out_wait_bypass	std_logic := ' 0 '
time_out_wait_bypass_s3	std_logic := ' 0 '
refclk_lost	std_logic
time_out_adapt	std_logic := ' 0 '
adapt_count_reset	std_logic := ' 0 '
adapt_count	integer range 0 to WAIT_TIME_ADAPT- 1
data_valid_sync	std_logic := ' 0 '
plllock_sync	std_logic := ' 0 '
phalignment_done_sync	std_logic := ' 0 '
fsmCnt	std_logic_vector ( 15 downto 0 )

Attributes
dont_touch	string
dont_touch	signal is " TRUE "
KEEP_HIERARCHY	string
KEEP_HIERARCHY	label is " TRUE "

Instantiations
synchronizer_run_phase_alignment	Synchronizer <Entity Synchronizer>
synchronizer_fsm_reset_done	Synchronizer <Entity Synchronizer>
synchronizer_soft_reset	SynchronizerEdge <Entity SynchronizerEdge>
synchronizer_rxresetdone	Synchronizer <Entity Synchronizer>
synchronizer_time_out_wait_bypass	Synchronizer <Entity Synchronizer>
synchronizer_mmcm_lock_reclocked	Synchronizer <Entity Synchronizer>
synchronizer_data_valid	Synchronizer <Entity Synchronizer>
synchronizer_plllock	Synchronizer <Entity Synchronizer>
synchronizer_phalignment_done	Synchronizer <Entity Synchronizer>

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The documentation for this design unit was generated from the following file:

• xilinx/7Series/gth7/rtl/Gth7RxRst.vhd