GigEthGtp7Wrapper.mapping Architecture Reference

Architecture >> GigEthGtp7Wrapper::mapping

Signals
gtClk	sl
gtClkDiv2	sl
selGtClk	sl
gtClkBufg	sl
refClk	sl
refRst	sl
sysClk125	sl
sysRst125	sl
sysClk62	sl
sysRst62	sl
qPllOutClk	slv ( 1 downto 0 )
qPllOutRefClk	slv ( 1 downto 0 )
qPllLock	slv ( 1 downto 0 )
qPllRefClkLost	slv ( 1 downto 0 )
qpllRst	slv ( NUM_LANE_G- 1 downto 0 )
qpllReset	slv ( 1 downto 0 )
dummySig	slv ( 1 downto 0 )

Instantiations
ibufds_gte2_inst	ibufds_gte2
bufg_inst	bufg
pwruprst_inst	PwrUpRst <Entity PwrUpRst>
u_mmcm	ClockManager7 <Entity ClockManager7>
u_gtp7quadpll	Gtp7QuadPll <Entity Gtp7QuadPll>
u_gigethgtp7	GigEthGtp7 <Entity GigEthGtp7>

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The documentation for this design unit was generated from the following file:

• ethernet/GigEthCore/gtp7/rtl/GigEthGtp7Wrapper.vhd