GearboxTb.sim Architecture Reference

Architecture >> GearboxTb::sim

Processes
tb
PROCESS_40	( clk32 )
tb
PROCESS_110	( clk32 )

Libraries
surf

Constants
TPD_G	time := 1 ns
INPUT_WIDTH_G	natural := 10
OUTPUT_WIDTH_G	natural := 8

Signals
clk32	sl := ' 0 '
rst32	sl := ' 0 '
clk66	sl := ' 0 '
rst66	sl := ' 0 '
input	slv ( INPUT_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
slaveData_0	slv ( INPUT_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
slaveValid_0	sl := ' 0 '
slaveReady_0	sl := ' 0 '
masterData_0	slv ( OUTPUT_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
masterValid_0	sl := ' 0 '
masterReady_0	sl := ' 0 '
slip_0	sl := ' 0 '
startOfSeq_0	sl := ' 0 '
masterData_1	slv ( INPUT_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
masterValid_1	sl := ' 0 '
masterReady_1	sl := ' 1 '
slip_1	sl := ' 0 '
startOfSeq_1	sl := ' 0 '
slip	sl := ' 0 '
slipCnt	slv ( 6 downto 0 ) := ( others = > ' 0 ' )

Instantiations
u_fifoasync_1	FifoAsync <Entity FifoAsync>
u_gearbox_0	Gearbox <Entity Gearbox>
u_gearbox_1	Gearbox <Entity Gearbox>
u_clkrst_1	ClkRst <Entity ClkRst>
u_clkrst_2	ClkRst <Entity ClkRst>
u_gearbox_test	Gearbox <Entity Gearbox>
u_fifoasync_1	FifoAsync <Entity FifoAsync>
u_gearbox_0	Gearbox <Entity Gearbox>
u_gearbox_1	Gearbox <Entity Gearbox>
u_clkrst_1	ClkRst <Entity ClkRst>
u_clkrst_2	ClkRst <Entity ClkRst>
u_gearbox_test	Gearbox <Entity Gearbox>

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The documentation for this design unit was generated from the following files:

• base/general/tb/GearboxTb.vhd
• build/SRC_VHDL/surf/GearboxTb.vhd