FwftCntTbSubModule.rtl Architecture Reference

Architecture >> FwftCntTbSubModule::rtl

Processes
comb	( dout , full , overflow , r , rd_data_count , rst , underflow , valid , wr_data_count )
seq	( clk )
comb	( dout , full , overflow , r , rd_data_count , rst , underflow , valid , wr_data_count )
seq	( clk )

Constants
ADDR_WIDTH_C	positive := ite ( MEMORY_TYPE_G = " distributed " , 5 , 9 )
DATA_WIDTH_C	positive := ADDR_WIDTH_C+ 1
REG_INIT_C	RegType := ( passed = > ' 0 ' , failed = > ' 0 ' , wr_en = > ' 0 ' , din = > ( others = > ' 0 ' ) , rd_en = > ' 0 ' , state = > IDLE_S )

Types
StateType	( IDLE_S , WRITE_S , WR_WAIT_S , READ_S , RD_WAIT_S , FAILED_S , PASSED_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
wr_en	sl := ' 0 '
din	slv ( DATA_WIDTH_C- 1 downto 0 ) := ( others = > ' 0 ' )
wr_data_count	slv ( ADDR_WIDTH_C- 1 downto 0 ) := ( others = > ' 0 ' )
wr_ack	sl := ' 0 '
overflow	sl := ' 0 '
prog_full	sl := ' 0 '
almost_full	sl := ' 0 '
full	sl := ' 0 '
not_full	sl := ' 0 '
rd_en	sl := ' 0 '
dout	slv ( DATA_WIDTH_C- 1 downto 0 ) := ( others = > ' 0 ' )
rd_data_count	slv ( ADDR_WIDTH_C- 1 downto 0 ) := ( others = > ' 0 ' )
valid	sl := ' 0 '
underflow	sl := ' 0 '
prog_empty	sl := ' 0 '
almost_empty	sl := ' 0 '
empty	sl := ' 0 '

Records
RegType

Instantiations
u_fifo	Fifo <Entity Fifo>
u_fifo	Fifo <Entity Fifo>

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The documentation for this design unit was generated from the following files:

• base/fifo/tb/FwftCntTbSubModule.vhd
• build/SRC_VHDL/surf/FwftCntTbSubModule.vhd