FirFilterSingleChannelWrapper Entity Reference

Inheritance diagram for FirFilterSingleChannelWrapper:

Collaboration diagram for FirFilterSingleChannelWrapper:

Entities
FirFilterSingleChannelWrapper.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
NUM_TAPS_G	positive := 3
SIDEBAND_WIDTH_G	positive := 1
DATA_WIDTH_G	positive := 8
COEFF_WIDTH_G	positive range 1 to 32 := 4

Ports
clk	in	sl
rst	in	sl
ibValid	in	sl
ibReady	out	sl
din	in	slv ( DATA_WIDTH_G- 1 downto 0 )
sbIn	in	slv ( SIDEBAND_WIDTH_G- 1 downto 0 )
obValid	out	sl
obReady	in	sl
dout	out	slv ( DATA_WIDTH_G- 1 downto 0 )
sbOut	out	slv ( SIDEBAND_WIDTH_G- 1 downto 0 )
S_AXI_ACLK	in	std_logic
S_AXI_ARESETN	in	std_logic
S_AXI_AWADDR	in	std_logic_vector ( 8 downto 0 )
S_AXI_AWPROT	in	std_logic_vector ( 2 downto 0 )
S_AXI_AWVALID	in	std_logic
S_AXI_AWREADY	out	std_logic
S_AXI_WDATA	in	std_logic_vector ( 31 downto 0 )
S_AXI_WSTRB	in	std_logic_vector ( 3 downto 0 )
S_AXI_WVALID	in	std_logic
S_AXI_WREADY	out	std_logic
S_AXI_BRESP	out	std_logic_vector ( 1 downto 0 )
S_AXI_BVALID	out	std_logic
S_AXI_BREADY	in	std_logic
S_AXI_ARADDR	in	std_logic_vector ( 8 downto 0 )
S_AXI_ARPROT	in	std_logic_vector ( 2 downto 0 )
S_AXI_ARVALID	in	std_logic
S_AXI_ARREADY	out	std_logic
S_AXI_RDATA	out	std_logic_vector ( 31 downto 0 )
S_AXI_RRESP	out	std_logic_vector ( 1 downto 0 )
S_AXI_RVALID	out	std_logic
S_AXI_RREADY	in	std_logic

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The documentation for this design unit was generated from the following file:

• dsp/generic/wrappers/FirFilterSingleChannelWrapper.vhd