FifoXpm.mapping Architecture Reference

Architecture >> FifoXpm::mapping

Processes
PROCESS_29	( rd_data_count_xpm , wr_data_count_xpm )

Constants
READ_MODE_C	string := ite ( FWFT_EN_G , " fwft " , " std " )
DOUT_INIT_C	string := " 0 "
MIN_THRES_C	positive := 8
MAX_THRES_C	positive := 2 ** ADDR_WIDTH_G- 8
WAKEUP_TIME_C	integer := 0
FIFO_WRITE_DEPTH_C	positive := 2 ** ADDR_WIDTH_G
FIFO_READ_LATENCY_C	natural := ite ( FWFT_EN_G , 0 , 1 )
FULL_RESET_VALUE_C	natural := 1
COUNT_WIDTH_C	positive := ite ( FWFT_EN_G , ADDR_WIDTH_G+ 1 , ADDR_WIDTH_G )
FULL_THRES_C	positive := ite ( ( FULL_THRES_G< MIN_THRES_C ) , MIN_THRES_C , ite ( ( FULL_THRES_G> MAX_THRES_C ) , MAX_THRES_C , FULL_THRES_G ) )
EMPTY_THRES_C	positive := ite ( ( EMPTY_THRES_G< MIN_THRES_C ) , MIN_THRES_C , ite ( ( EMPTY_THRES_G> MAX_THRES_C ) , MAX_THRES_C , EMPTY_THRES_G ) )
USE_ADV_FEATURES_C	string := " 1F1F "

Signals
reset	sl
sRdEn	sl
sValid	sl
dout_xpm	slv ( DATA_WIDTH_G- 1 downto 0 )
wr_data_count_xpm	slv ( COUNT_WIDTH_C- 1 downto 0 )
wr_ack_xpm	sl
overflow_xpm	sl
prog_full_xpm	sl
almost_full_xpm	sl
full_xpm	sl
rd_data_count_xpm	slv ( COUNT_WIDTH_C- 1 downto 0 )
underflow_xpm	sl
prog_empty_xpm	sl
almost_empty_xpm	sl
empty_xpm	sl

Instantiations
u_fifo	xpm_fifo_async
u_reset	RstSync <Entity RstSync>
u_fifo	xpm_fifo_sync
u_pipeline	FifoOutputPipeline <Entity FifoOutputPipeline>

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The documentation for this design unit was generated from the following files:

• base/fifo/rtl/dummy/FifoXpmDummy.vhd
• base/fifo/rtl/xilinx/FifoXpm.vhd